1. Field of the Invention
The present invention relates in general to a semiconductor device and a method of manufacturing the same. More particularly, the present invention is directed to an enhancement mode MOSFET device and methods of manufacturing the same.
2. Description of the Related Art
Increasing the density of integration of a semiconductor device requires shortening of channel length of MOS transistors. If the channel length of the MOS transistor is shortened, a significant leakage current flows even though a voltage lower than a threshold voltage is applied to a gate of the MOS transistor. A high leakage current flow through the semiconductor device made of the MOS transistors, in the stand-by condition, leads to a high power consumption. Several methods, such as reducing the thickness of a gate dielectric layer or increasing the channel ion implantation concentration etc, have been tried for solving this short channel effect problem of the MOS transistor.
However, these conventional methods also cause a change in the threshold voltage of the MOS transistor, making it difficult to optimize the thickness of the gate dielectric layer and the channel ion implantation concentration. Therefore, an attempt to solve the short channel effect through a lightly doped drain/source (LDD) structure is underway instead of the above stated approaches.
The MOS transistor having the conventional LDD structure has a large overlap area between the source/drain and the gate, and consequently a large overlap capacitance. The conventional LDD structure also introduces a significant leakage current in the MOS transistor by a gate induced drain leakage (GIDL) effect. In the GIDL effect, a tunneling current is generated between the drain region and its adjacent channel region even when the MOS transistor is in ‘Off’ state. Such a large leakage current may cause an error operation of a PMOS transistor.